EUV The Focal Point

EUV The Focal Point is your Extreme Ultraviolet (EUV) lithography podcast. Industry Briefings: Cover leading-edge nodes, DRAM, HBM and strategy moves from ASML & co. and from the end customers Apple & co. Focus Deep Dives: Unpack physics, plasma, optics and how EUV scanners really work. Hosted by EUV experts Samantha and Jack, built entirely with AI (a technology that itself relies on EUV-made chips ;-) using company newsrooms, Wikipedia and news sites. AI can make mistakes: always verify the information independently before using it as a basis for business decisions.

EUV The Focal Point is a technology podcast hosted by Unknown Host, with 57 episodes on record and a Required Pod Score of 80. PitchCentric scores this show on Booking Probability, Listen Score, and live audience signals refreshed every 24 hours.

Unknown Host hosts EUV The Focal Point, a technology show with 57 episodes published.

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  Episode #58

  [058] Industry briefing - EUV The Focal Point

  Aug 18, 202615 minS1

  This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Samsung’s revised foundry roadmap puts High-NA EUV around the 1-nanometer-class generation in 2030 while extending the life of its Low-NA EUV platform. At the same time, record equipment spending, new equity financing, and packaging investments show that the economic race is increasingly about sequencing capital across the whole manufacturing system rather than adopting one tool first. Key takeaways - Samsung reportedly moved SF1.4 from a 2027 target to 2029 and plans High-NA EUV insertion with its 1-nanometer-class process around 2030. - Samsung’s roadmap implies continued Low-NA EUV use for SF1.4+ while the company concentrates near-term resources on the SF2 family. - Applied Materials reported record fiscal Q3 2026 revenue of $9.12 billion, up 25% year over year, and guided fiscal Q4 revenue to about $10.25 billion, plus or minus $500 million. - Applied Materials raised its calendar-2026 advanced-packaging growth expectation to more than 70%, reinforcing the broader process-equipment signal highlighted in the August 4 outlook. - Intel upsized its common-stock offering from $15 billion to $20 billion and expects approximately $19.7 billion of net proceeds; the company says proceeds may include capital expenditures and working capital. - TSMC approved about $29.44 billion of capital appropriations covering advanced technology, advanced packaging, specialty capacity, fabs, and facility systems. - TSMC and Sony signed a definitive agreement for a next-generation image-sensor joint venture in Kumamoto, with volume production targeted for 2029. - SPIL reportedly broke ground on a nearly NT$100 billion Douliu plant that will add CoWoS capacity, with first-phase operations planned for 2028. - Nanya Technology says it is evaluating potential expansion sites but has not made a decision on reported new fabs in Yunlin and Pingtung. - U.S. policy pressure is increasingly reaching foundries themselves, with lawmakers pushing stricter scrutiny of advanced-chip orders that could indirectly serve sanctioned Chinese firms. Glossary Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light for critical patterning at advanced semiconductor nodes. High Numerical Aperture (High-NA) EUV — The newer EUV platform intended for tighter critical-layer patterning and selective future-node insertion. Low Numerical Aperture (Low-NA) EUV — The established 0.33-NA EUV platform used broadly in current advanced logic and memory production. SF2 — Samsung Foundry’s 2-nanometer-class process family. SF1.4 — Samsung Foundry’s 1.4-nanometer-class process generation, now reported for 2029. Intel 14A — Intel Foundry’s next-generation process platform planned after Intel 18A. CoWoS — Chip on Wafer on Substrate, an advanced packaging approach used for large AI accelerators and HBM integration. HBM — High Bandwidth Memory, stacked memory used with advanced AI and high-performance computing processors. DRAM — Dynamic Random-Access Memory, the volatile memory technology underlying mainstream memory products and HBM.

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  Episode #57

  [057] Deep Dive Topic - New Ways to Store Bits

  Aug 13, 202626 minS1

  This post was created using AI. Please check the information if you want to use it as a basis for decision-making. EPISODE TEASER Why is the memory industry exploring RRAM, MRAM, and new DRAM concepts when SRAM, DRAM, and NAND already work so well? This episode explains the physical storage mechanisms, the engineering trade-offs, and the most realistic application paths. It also clarifies why “DRAM+” is an umbrella term rather than one standardized memory technology. KEY TAKEAWAYS - Every memory tier trades speed, density, energy, endurance, retention, cost, and integration complexity. - Conventional DRAM stores charge in a capacitor and must refresh it because the charge leaks away. - “DRAM+” can describe enhanced DRAM approaches such as HBM, gain-cell or capacitorless DRAM, three-dimensional integration, embedded DRAM, and processing near the memory. - RRAM stores information as resistance by moving ions or defects in a switching layer; variability is one of its central challenges. - STT-MRAM writes through a magnetic tunnel junction, while SOT-MRAM separates the read and write paths. - Nonvolatile memories reduce standby and refresh energy, but active write energy and peripheral circuits still matter. - RRAM and MRAM can support compute-in-memory, but array parasitics, data conversion, write control, and device variation limit idealized gains. - Advanced DRAM is the strongest near-term route for main memory; MRAM and RRAM are more likely to expand first in embedded and specialized roles. - The likely future is a more heterogeneous memory hierarchy, not one universal replacement. GLOSSARY DRAM — Dynamic random-access memory. Volatile memory that usually stores each bit as charge in a capacitor and requires periodic refresh. DRAM+ — A nonstandard umbrella term used here for enhanced DRAM cells, architectures, packaging, stacking, and processing-near-memory concepts. SRAM — Static random-access memory. Fast volatile memory commonly used for processor caches; a typical cell uses several transistors. NAND flash — Dense nonvolatile storage that retains data without power and is programmed and erased in larger groups than RAM. RRAM or ReRAM — Resistive random-access memory. Nonvolatile memory that stores data in different resistance states. MRAM — Magnetoresistive random-access memory. Nonvolatile memory that stores data in magnetic orientation and reads it through a resistance difference. STT-MRAM — Spin-transfer torque MRAM. A form of MRAM in which write current passes through the magnetic tunnel junction. SOT-MRAM — Spin-orbit torque MRAM. A form of MRAM with a separate lateral write path that acts on the magnetic free layer. Crossbar array — A grid of crossing conductors with a memory element at each intersection; useful for dense storage and parallel analog operations. Compute-in-memory — An architecture that performs selected operations in or very near memory arrays to reduce data movement.

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  Episode #56

  [056] Industry briefing - EUV The Focal Point

  Aug 10, 202611 minS1

  This post was created using AI. Please check the information if you want to use it as a basis for decision-making. Nanya Technology has turned EUV memory expansion into a funded fab schedule, while TeraFab has gained a confirmed Texas site and an initial investment figure. AMD and TSMC provide fresh demand-side evidence, and reported Chinese-tool evaluations by Samsung and SK hynix show how export controls can reshape equipment qualification beyond lithography. Key takeaways - Nanya approved up to NT$346.6 billion of Fab 5A capital expenditure for 2026-2029, including EUV equipment. - Fab 5A is designed for 45,000 wafer starts per month, with first-phase capacity targeted at 35,900 WSPM. - Nanya plans wafer input in the second half of 2027, with 30,000 WSPM targeted for 2028 and 35,900 WSPM for 2029. - SpaceX and Tesla identified Grimes County, Texas, as the TeraFab site and announced an initial investment of $16.8 billion. - TeraFab still has no disclosed EUV scanner count, mask strategy, detailed process flow, or public production qualification schedule. - AMD reported Q2 2026 revenue of $11.5 billion; Data Center revenue was $6.7 billion, up 107% year over year. - TSMC reported July 2026 revenue of NT$467.58 billion, up 44.7% year over year. - Reuters reported evaluations of AMEC etch tools by Samsung and SK hynix, while both companies denied testing AMEC equipment for use in China and no broad deployment decision was reported. Glossary Extreme Ultraviolet (EUV) — Advanced lithography using 13.5-nanometer light for critical semiconductor patterning. Dynamic Random-Access Memory (DRAM) — Volatile memory used widely in servers, PCs, mobile devices, and AI systems. Wafer starts per month (WSPM) — A fab-capacity measure describing how many wafers enter production each month. 1C / 1D / 1E DRAM — Successive 10-nanometer-class DRAM process generations in Nanya’s roadmap. Capital expenditure (capex) — Spending on long-lived manufacturing assets such as fabs and production equipment. Etch — A semiconductor process that selectively removes material to transfer patterns into underlying layers. Mask strategy — The plan for photomasks and patterning steps used to manufacture a chip design. Process flow — The ordered sequence of fabrication steps used to build semiconductor devices.

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  Episode #55

  [055] Deep Dive Topic - Recap of H1 2026

  Aug 5, 20269 minS1

  This post was created using AI. Please check the information if you want to use it as a basis for decision-making. In this H1 2026 review, EUV lithography is examined not as a single-machine breakthrough, but as the coordinating system behind AI-driven semiconductor manufacturing. The episode covers Low-NA productivity, the selective economic case for High-NA, rising HBM demand, advanced packaging, mask and metrology constraints, and the global expansion of leading-edge fabs. The central question is no longer who can print the smallest feature, but who can convert scarce tools, photons, engineering capacity, and cleanroom space into reliable compute at scale.

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  Episode #54

  [054] Industry briefing - EUV The Focal Point

  Aug 4, 202620 minS1

  This post was created using AI. Please check the information if you want to use it as a basis for decision-making. This week’s episode looks beyond the EUV scanner to the design and manufacturing tools that turn advanced patterns into profitable silicon. SK hynix’s HBM4 ramp, strong results from Lam Research and KLA, and certified Synopsys flows for Intel 14A all point to the same conclusion: process integration and yield control are becoming as strategic as exposure capacity. Key takeaways - SK hynix reported second-quarter revenue of 79.3 trillion won and operating profit of 60.5 trillion won. - SK hynix began mass shipments of HBM4 in the second quarter and plans to ramp production in the second half of 2026. - SK hynix has finalized long-term agreements with around 10 customers and is accelerating the M15X mass-production schedule. - Lam Research reported record quarterly revenue of 6.72 billion dollars and guided the September quarter to about 8.1 billion dollars, plus or minus 400 million dollars. - KLA reported quarterly revenue of 3.66 billion dollars and guided the September quarter to 4.0 billion dollars, plus or minus 200 million dollars. - Synopsys certified AI-powered EDA and multiphysics flows for Intel 14A, including support across silicon, packaging, thermal, power-integrity, and electromagnetic analysis. - High-NA EUV economics depend on the full manufacturing flow, including masks, resists, etch transfer, metrology, design rules, and packaging. - Reuters reported that China has begun producing domestically developed immersion DUV lithography systems, although high-volume reliability and performance remain unproven. - No new official EUV scanner shipment count was identified this week; the strongest signals came from the surrounding equipment and design ecosystem. Glossary Extreme Ultraviolet (EUV) — Lithography using 13.5-nanometer light to pattern the most advanced semiconductor layers. High Numerical Aperture (High-NA) EUV — A higher-resolution EUV platform intended for selected critical layers at future advanced nodes. Deep Ultraviolet (DUV) — Lithography using longer-wavelength ultraviolet light; immersion DUV remains important across mature and advanced process flows. High Bandwidth Memory (HBM) — Vertically stacked memory designed to provide very high data bandwidth for AI and high-performance computing. Dynamic Random-Access Memory (DRAM) — Volatile working memory used in servers, computers, mobile devices, and HBM stacks. Electronic Design Automation (EDA) — Software used to design, verify, optimize, and prepare chips for manufacturing. Design Technology Co-Optimization (DTCO) — Joint optimization of chip design rules and process technology. Process control — Inspection, metrology, analytics, and feedback used to maintain yield and manufacturing stability. Multiphysics analysis — Combined modeling of electrical, thermal, mechanical, and electromagnetic effects in a chip and package.

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